Bit-Serial Digital Filter Implementation using a Custom C Compiler

Bit-serial arithmetic offers the potential for more compact designs and increased levels of functional parallelism in comparison to bit-parallel arithmetic. While these advantages come at the expense of decreased throughput, there are areas of digital signal processing where the trade-off is desirable. Unfortunately, designers often overlook bit-serial arithmetic, partly due to a lack of design tools. This paper describes the design and implementation of a compiler which generates bit-serial designs from a high-level language based on C. The compiler targets a synthesizable VHDL bit-serial library, relying on a conventional VHDL backend for placement and routing. To exploit the relative low hardware cost of bit-serial operations, the compiler employs techniques developed for conventional optimizing compilers to extract fine-grained parallelism from high-level algorithms. Working from a high-level description of an algorithm, a designer can generate different design implementations from a single version of the source, using a parameterizable system word length, or by specifying a compiler option to trade-off latency for reduced parallelism, and therefore reduced hardware cost.