Two-Stage Resistor-Load Logic for Digital Applications on Flexible Substrates

A new standard cell topology, two-stage resistor-load logic, for Indium-Gallium-Zinc-Oxide (IGZO) thin-film transistor (TFT) technology is presented. The proposed inverter topology is compared with conventional one-stage resistor-load gates in terms of robustness (noise margin), speed performance and power consumption. It has been shown that the two-stage resistor-load logic style is more robust against process variations and demonstrates higher speed performance. As a proof of concept, a 4-bit digital multiplier circuit on a flexible substrate is designed and fabricated with 1.66 mm2 area using 800 nm channel length n-type only TFTs. Measured power consumption of the chip is less than 12 mW with 1 MHz of operating clock frequency.1