LDO Optimization with Evolutionary Neural Network

In this paper, a low voltage low dropout (LDO) regulator is designed and simulated in 0.18µm CMOS technology, which converts an input voltage of 1.4V into a stable regulated output voltage of 1.2 V using H-Spice circuit simulator. The proposed LDO structure is based on Output Voltage Spike Reduction (OVSR) circuits and capacitance compensation circuits to enable a fast-transient response with ultra-low power dissipation and to make the LDO stable for a wide range of output load currents (0–50 mA). Here, the Artificial Neural network (ANN) algorithm is demonstrated for solving the problem of the device sizing and optimization. This approach for designing handles non-linear effects of sub-micron devices very effectively. The Simulation results verify that the transient times are less than 2.8 µs and the maximum undershoot and overshoot are 20 mV while consuming only 26 µA quiescent current. The proposed LDO is stable with an on-chip capacitor at the output node within the wide range of 1-100 PF.