A 6.22pJ/conv-step Split Design and Subtractor Based Binary Search ADC

This paper presents the design of 8-bit asynchronous based binary search analog to digital converter (ADC) using split design topology. In the proposed work, the 8 bits had been realized using two stages of 4 bits each with a subtractor in between. The use of such asynchronous design had resulted in reduction of switching network, reduced number of comparator and improvement in speed and chip area. The proposed 8-bit ADC is designed in 0.18 μm CMOS process and realizes conversion rate of approximately 230 MS/s while consuming 11.5 mW of power with 50% saving of chip area and 16% improvement of speed in comparison to other design. The proposed design achieves 6.22 pJ/conv-step of Walden FOM.