A method of pipeline optimization for reconfigurable task

Reconfigurable computing is seen as an effective solution that combines the high flexibility of traditional processors with the high processing efficiency of ASIC. The delay caused by the GPC or RPU that is caused by reconfiguration in the reconfigurable system is called the configuration delay, and the configuration delay is purely performance overhead. Previous studies have proposed a number of different ways from the device layer to the application layer to reduce or hide the reconfiguration latency, but not a good solution to this problem. This paper realizes the pipeline of applications when they are reconstructed and configured on the FPGA platform, thus providing the efficiency of application execution and the flexibility of refactoring.