Low power mapping optimization of loops for dual-Vdd CGRAs

Coarse Grained Reconfigurable Architecture (CGRA) is a promising platform based on its high performance and low power. Efficient compilers have been developed for improving loop mapping performance using modulo scheduling, and the Dual-Vdd technique is popularly used to reduce power consumption in CGRAs. To achieve the best mapping performance and lowest power consumption simultaneously, this paper formulates a joint optimization problem of performance and power efficiency of CGRAs and proposes a low power optimization approach integrating Dual-Vdd assignment into the loop pipelining mapping. The experimental results show that the proposed optimization approach could reduce the power by 22.5% on average without decreasing performance.