Arreglo de Microelectrodos Planares con Procesos CMOS Estándar (Semiconductor Complementario Metal-Oxido)

The design and the on-chip integration of planar microelectronic array and the read-out circuit implemented by 0.6 µm CMOS process (Complementary Metal–Oxide–Semiconductor), is presented. The design includes a shielding ring around the microelectrode array and a control for a tunable low pass filter, which are made with a CMOS transmission gate operating in subthreshold region. This is achieved by varying the gate voltage in a range from 400 to 800 mV for a frequency range of 1 to 1KHz. The performance of the circuit with a voltage supply ± 1.5 V was 40dB gain, 44 dB PSRR (power supply rejection ratio) and 87 dB CMRR (common-mode rejection ratio), in an area of 0.014mm 2 , showing that the system is a good alternative for biological applications.