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A 1.5-ns access time, 78-μm2 memory-cell size, 64-kb ECL-CMOS SRAM
A 1.5-ns access time, 78-μm2 memory-cell size, 64-kb ECL-CMOS SRAM
1992
Kunihiko Yamaguchi
H. Nambu
Kazuo Kanetani
Youji Idei
Noriyuki Homma
Toshiro Hiramoto
Nobuo Tamba
K Watanabe
Masanori Odaka
T. Ikeda
K. Ohhata
Yoshiaki Sakurai
Keywords:
Electronic engineering
Computer science
cell network
Emitter-coupled logic
Circuit design
Memory cell
Electrical engineering
Static random-access memory
CMOS
Access time
Logic gate
Correction
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