True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits

A method is proposed for testability analysis of digital circuits focusing on calculating the probabilistic controllability measures in terms of signal probabilities, when random or pseudorandom patterns are applied to the circuit inputs. The tasks of calculating the probabilistic observability and testability measures are transformed into the task of calculating the controllability. The structure of the circuit is presented as a set of Structurally Synthesized BDDs (SSBDD), which allows controllability analysis with higher speed than carrying out calculations on the gate-level, retaining the possibilities of assessment of the controllability of all gate-level nodes represented by related SSBDD nodes. The proposed method is based on tracing true paths in SSBDDs. A general case is considered, where the circuit may include redundancies. It is shown that the known methods of calculating signal probabilities, which are not taking into account the redundancy in circuits, are not accurate. A method is proposed for proving the redundancy of faults, which is based on the same idea of SSBDD path tracing. Experimental results show higher accuracy and higher speed of SSBDD-based probability calculations, compared to gate-level calculation.