Manufacture of field effect trench transistor array

PURPOSE: To improve access performance, by forming thick oxide on a drain bonding part and all over the upper part of a source bonding part by using a nitride side wall spacer, and reducing coupling capacitance. CONSTITUTION: An N - epitaxial layer 12 is formed on an N + substrate 10, and a P well region 15 is formed on the N - epitaxial layer 12. An oxide isolation trench region 16 is formed on the surface, and N ++ diffusion region 18 is formed. A trench 20 is etched as far as the inside of the region 15. P + doping is performed to the side wall of the trench 20 by a slant directional ion implanting method. A silicon nitride side wall spacer 22 is formed on the side wall of the trench 20. A self alignment type slight dope bonding part 24 and a buried N + source bonding part 26 are formed by using a low slant directional ion implanting method. Rather a thick oxide layer 16A is formed. The spacer 22 is eliminated, and a thin gate oxide layer 30 is grown. The trench 20 is filled with N + poly Si, and a transfer gate 22 and a word line 33 are formed by patterning. COPYRIGHT: (C)1991,JPO