Dynamic partial reconfiguration verification using assertion based verification

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software Defined Radio (SDR) in a reasonable area. However, utilizing DPR needs extra care to be taken for new issues such as waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. This paper proposes a technique to verify these newly introduced issues using Assertion Based Verification (ABV). The proposed technique proves effectiveness in finding issues on real designs that utilize DPR technique.