A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6- mu m triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0*1.8 mu m/sup 2/ has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11*6.95 mm/sup 2/, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm/sup 2/ by using the minimal cell size (2.0*10 mu m/sup 2/). >