A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

This paper describes a second generation 1.2 V high performance 0.13 /spl mu/m SOI technology. Aggressive ground rules and a tungsten damascene local interconnect render the densest 6T 0.13 /spl mu/m SRAM reported to date with a cell area of 1.80 /spl mu/m/sup 2/. 248 nm lithography is used for all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced BEOL process with low-k interlevel dielectrics and SiC barrier layers.