Vertical Ge and GeSn heterojunction gate-all-around tunneling field effect transistors

Abstract We present experimental results on the fabrication and characterization of vertical Ge and GeSn heterojunction Tunneling Field Effect Transistors (TFETs). A gate-all-around process with mesa diameters down to 70 nm is used to reduce leakage currents and improve electrostatic control of the gate over the transistor channel. An I ON  = 88.4 μA/μm at V DS  =  V G  = −2 V is obtained for a TFET with a 10 nm Ge 0.92 Sn 0.08 layer at the source/channel junction. We discuss further possibilities for device improvements.