Cmos transistor logic circuit using strain si/sige hetero structure layer

PURPOSE: To enable both an n-type device and a p-type device to be formed as a common planar structure, by forming a semiconductor layer receiving a tensile strain and a semiconductor layer receiving a compressive strain on a semiconductor substrate. CONSTITUTION: A field effect transistor has a planar hetero structure 22 composed of a plurality of layers 23. The planar hetero structure 22 consists of a first ease Si1-x Ge layer 34 of a Ge molar fraction (x) in a range of 0.2-0.5, an Si layer 32 receiving a tensile strain, a thin ease layer SiGe layer 40, and an SiGe layer 30 receiving a compression strain and having a Ge molar fraction (y) in a range of 0.5-1.0. In this case, y-x is larger than 0.2. The Si layer 32 receiving the tensile strain acts as an n-type channel for an n-type field effect transistor, and the SiGe layer 30 receiving the compressive strain acts as a p-type channel for a p-type field effect transistor. Therefore, the n-type device and p-type device can be utilized as a common planar structure.