Multiple Bit Upsets and Error Mitigation in Ultra-Deep Submicron SRAMS

Recent measurements of the SEU (single-event upset) cross-section for 6 T SRAMs fabricated in a nano-scale commercial CMOS process were performed. Results indicated that the dominant upset mechanism was associated with multiple-cell upsets (MCUs) strikes on PMOS transistors. The dominance of the MCU cross section favors the use of a block architecture with widely spaced word bits and the use of EDAC (error detect and correct) along with periodic memory scrubbing to prevent the integration of single-bit errors.