Guarding the guards: Enhancing LNS performance for common applications

The rounding modes of floating point arithmetic are usually simplified in implementations of alternative number systems, including the Logarithmic Number System (LNS), to a single round-to-nearest mode requiring internal guard bits that are exponentially expensive to provide. Noting that rounding takes significant time and hardware, this paper describes two innovations that enhance LNS performance, and we analyze the possible improvements for FFT, matrix inversion, and other application-specific examples where dedicated processor hardware may be preferred.