A Reconfigurable Passive Switched-Capacitor Multiply-and-Accumulate Unit for Approximate Computing

A reconfigurable switched-capacitor based multiply and accumulate unit (MACU) is proposed in this work. The multiplication is achieved by a digital-to-capacitance converter (DCC) with a flexible weight resolution of 2-6 bits. The accumulation output is digitized using a reconfigurable 6-9 bit successive approximation register analog to digital converter (SAR ADC). The design is implemented in 65nm CMOS process. The power consumption tends to reduce with the reduction of ADC resolution. The proposed MACU achieved an efficiency of 20.83 TOPS/W at an output resolution of 6. Simulation results for edge detection, MNIST image classification, and speech denoising are presented to prove the effectiveness of the proposed unit.