0.13 µm Metal-Oxide-Nitride-Oxide-Semiconductor Single Transistor Memory Cell with Separated Source Line

A 0.13 µm metal (conductive gate) oxide nitride oxide semiconductor (MONOS) single transistor memory cell is proposed and demonstrated. The three main limiting factors and their solutions in a 0.13 µm MONOS single transistor memory cell with a separated source line are clarified. The first issue is the reduction in the margin of program inhibit voltage due to a short channel effect. This problem can be improved by applying a positive bias voltage to unselected wordlines. The second issue is the leakage current from unselected cells. This problem can be reduced by the use of a source bias read technique. The third issue is the read disturb of a selected cell. This problem can be improved with a thicker tunnel insulator without increase in program time. An experimental 0.13 µm MONOS memory cell is obtained with satisfactory results. A small cell size of about 6F2 (F: feature size) is proposed by the use of winding source lines.