A low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range

An 8-bit 100MSample/s folding/interpolating ADC is presented. Using a new method incorporating both P and N folding blocks. The input voltage range of the ADC is increased to 1.1V, with a supply voltage of 1.5V. Implemented in a 0.15 /spl mu/m digital CMOS process, simulation results show an INL below /spl plusmn/0.3 LSB, SNDR of 40.7dB at 100MHz sampling frequency and power dissipation of 35 mW.