Device characteristics of crystalline epitaxial oxides on silicon

There is an extensive effort in the transistor industry to develop an alternative high-k gate dielectric to replace SiO/sub 2/ due to tunneling limits. We have investigated the potential of crystalline perovskite oxides (SrTiO/sub 3/ or STO) grown epitaxially over Si as a gate dielectric. Transmission electron microscopy images show that these epitaxial STO films have an interfacial amorphous layer <10 /spl Aring/ thick, that is mostly SiO/sub 2/. Using tantalum nitride (TaN) as a gate electrode, capacitors and MOSFETs were fabricated. Films with an equivalent oxide thickness (EOT) of 9 /spl Aring/ were achieved from a 100 /spl Aring/ STO layer yielding a dielectric constant of /spl sim/160. Measurements on n- and p-channel MOSFETs show leakage currents at /spl plusmn/1 V beyond inversion of 15 mA/cm/sup 2/ and 25 mA cm/sup 2/ respectively. Drive currents of 245 and 20 /spl mu/A//spl mu/m were realized for n- and p-channel devices. Calculated field mobilities were 221 cm/sup 2//V-sec for electrons and 62 cm/sup 2//V-s for holes. The use of a gate stack that has a high-k material (STO) over a low-k material (SiO/sub 2/) may have some potential advantages over a single medium-k layer.