Design of high precision single channel TDC based on FPGA

High precision time measurement technology is the basis of many scientific applications. It plays an important role in radar, sonar, laser ranging, particle physics and other advanced scientific fields. Meanwhile, the ability of high-precision time measurement is also an important factor limiting the development of these fields. Time to digital conversion (TDC) is a commonly used time interval measurement method, which is widely used in the above-mentioned advanced areas. This paper presents a new TDC design method based on the delay chain structure, and the measurement accuracy is further improved by the combination of rough and exquisite counting. The theoretical basis of the TDC is described. The calculation formula of the total time to be measured is given. Then, by combining the start and the stop signal reasonably, the time of gate signal is within an acceptable range, which reduces the instability of the signal and the number of input signal sources. The designed TDC achieves excellent delay uniformity and stability through the reasonable layout and routing of Carry4 delay chain module in FPGA. In addition, in the design of latch unit, a two-stage latch unit is designed according to the mean time between failures (MTBF) theorem, which ensures the consistency of delay and the correctness of timing, avoids the generation of metastable state, and improves the timing accuracy. Finally, in order to verify the performance of the proposed TDC design scheme, reasonable post simulation and board level verification are conducted under different clock frequencies. The verification results show that the maximum mean error of TDC is 3.99ps and the minimum is 2.82ps.