Device-level compact modeling of perpendicular Nanomagnetic Logic for benchmarking purposes

We show that physical-based compact modeling of field-coupled magnets is highly suitable to benchmark perpendicular Nanomagnetic Logic for comparison with other beyond-CMOS device candidates. Compact models enable simulation of the device behavior depending on the magnet's geometry, material, fabrication variations, clocking speed, temperature and noise. Logic computing reliability of the device is determined by simulation, and common physical measures (area, power, delay) are extracted for benchmarking purposes. The computational throughput is calculated for comparison with CMOS and further emerging beyond-CMOS devices. As an example, a 1-bit full adder circuit is analyzed in terms of progressive scaling, clocking speed and material improvements. The results show that - in addition to the area reduction - scaling significantly decreases the computing error rate, and enables an increase in the clocking frequency, whereas material improvements reduce the power consumption. The computational throughput as a common measure for the performance of the full adder circuit is equivalent, or even higher than, full adder circuits in CMOS and other beyond-CMOS technologies.