Power-Gating Flip-Flops and Sequential Logic Circuits Using Single-Rail MCML

With the growing uses of portable computers, energy-efficient realizations with high speed operations have become more and more important for digital hardware. In this paper, the design methods of the power-gating single-rail MOS current mode logic (SRMCML) circuits are presented. A power-gating scheme for SRMCML flip-flops is presented. Flip-flops and a decimal counter based on the powergating SRMCML are used to verify the effectiveness of the proposed power-gating sequential structure by HSPICE simulations with a SMIC CMOS 130nm technology. The power dissipation and delay of these basic circuits have also been measured and presented. From the outcomes of simulation, it is shown that the energy loss and the power-delay products of the power-gating SRMCML circuits is smaller than corresponding static complementary CMOS alternatives.