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Design and Implementation of an Analog PLL-Based Clock and Data Recovery Circuit for High-Speed Serial Links
Design and Implementation of an Analog PLL-Based Clock and Data Recovery Circuit for High-Speed Serial Links
2014
Rushabh Mehta
Keywords:
CPU multiplier
Clock skew
Clock domain crossing
Synchronous circuit
Data recovery
Digital clock manager
Asynchronous circuit
Phase-locked loop
Electronic engineering
Computer science
data recovery circuit
Computer hardware
Correction
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