delivery method spacers has low permittivity

The present invention relates to a method of manufacturing a transistor from a stack comprising at least a grid pattern comprising at least one sidewall, characterized in that it comprises: - forming at least one grid spacer on the at least the sidewall of the gate pattern; - reduction, after an exposure step of the stack to a temperature greater than or equal to 600 ° C, the dielectric permittivity of the at least one grid spacer, said reducing step comprising at least one ion implantation (300 ) in at least part of the thickness of the at least one grid spacer.