Beyond the performance of 3D-Torus: Equality topology with low radix

With the rapid development of electronic products, the high-speed computing and the personal 3C terminal all make greater demands the on-chip performance. Due to the limited bandwidth, the low communication efficiency and the bad scalability, the Network on Chip (NoC) has been able to satisfy the requirements of the applications above. In this work, we present an innovative design concept for on-chip low-radix networks with a novel Equality topology against with the 3D-Torus (3DT). Besides of its application in chip design, Equality is a high-performance interconnect topology that is proposed for general purpose applications including supercomputing, data center, cloud service, and industrial cluster solutions. At present work, we have evaluated the performance of the target Equality networks with 3DT networks which are also low-radix (k = 6) designs via simulations carried out by BookSim 2.0 package. Our extensive evaluations show that Equality outperforms traditional low-radix topologies of 3DT in zero-load latency and maximum throughput under all ten traffic patterns studied in present work. In the systems of 4096 node, efficiency of Equality is of orders higher than that of 3DT. Our significant results also appear the network efficiencies of Equality topology seen to be better than 6D-torus/mesh for Fujitsu topology while its network is in global communication status.