Function-based ESD protection circuit design verification for BGA pad-ring array

This paper reports a new function-based on-chip electrostatic discharge (ESD) protection circuit design verification technique for integrated circuits (ICs) using ball grid ball (BGA) pad-ring array. The ESD protection design verification method is enabled by ESD simulation including ESD behavior modeling and BGS pad-ring metal routing evaluation through ESD extraction using the ESDExtractor CAD tool for whole-chip pad-ring array. Full function-based ESD protection design simulation and verification is applied to a visible light communication (VLC) transceiver IC using large BGA pad-ring array, which was implemented in a commercial 180nm BCD technology.