The Development of Paddle Shift Analysis for IC Packaging Processing

During IC packaging processes, defects such as warpage, paddle shift and wire sweep etc, may happen. There was little literature about paddle shift and wire sweep analyses while most research in the past were focusing on warpage phenomenon in package outline. Excessive paddle shift reduces the encapsulation protection for the components, and may result in failure due to excessive wire sweep and stress, then cause the signal breakdown or a short circuit. Computer-aided analysis is one of the feasible tools for simulating and predicting the occurrence of such defects in molding process, even prior to the commencement of mass production of a package. Because of several analyses, such as mold filling analysis, wire sweep analysis, paddle shift analysis, warpage analysis, and stress strain analysis need to be assembled in one simulation series, more than one mesh models are needed for the analysis during the overall IC packaging analysis. The number of elements of those mesh model are often more than 600,000. For such large mesh model, a high quality methodology of mesh generation would be used. Unbalance pressure between top and bottom cavities was used as the loading for the analysis. In this study, a thin small outline package TSOP-I 48L produced by ChipMOS Technologies Ltd., was used for paddle shift simulation. In the simulation results, the lead shift phenomenon agreed very well with the experiments. This example demonstrated the feasibility and usefulness of this approach.