Using verilog HDL to teach computer architecture concepts

Students in computer architecture courses, especially undergraduates, need to design computer components in order to gain an in-depth understanding of architectural concepts. For maximum benefit, students must be active learners, engage the material and design, i. e., produce components to meet a specific need. Unfortunately, computers have become so sophisticated that designing architectural components, e. g., a cache memory, in hardware is not feasible in a one semester course. This paper describes an approach where students use a hardware description language (HDL), Verilog HDL and an associated simulator, to design components of computer systems and explore architectural concepts. To support this approach, the author has developed web-based course materials which include a manual on Verilog HDL, a paper on how to realize his Verilog-based computational model in digital circuits and twelve structured laboratory exercises.