The design and optimization of gain-boosted OTA for high speed and high accuracy sample and hold amplifier

In this paper, a systematical method of designing a high gain and high speed gain-boosted operational transconductance amplifier (gain-boosted OTA) is introduced through mathematically modeling its small signal equivalent circuits in a simple and useful way. By applying root locus techniques to the conclusion of this model, two different ways of optimizing the performance of the gain-boosted OTA are proposed. To verifying the design methods, SMIC 0.18 mum CMOS technology and 1.8 V supply voltage are applied to implement this high gain and high speed OTA. The simulation results show that the output of the sample and hold amplifier (SHA) using these OTAs has minimized ring and overshoot, achieving SNR over 100 dB and SNDR over 70 dB with 39.9 MHZ sinusoid input, and at the higher frequency region, with input signal of 79.9 MHZ, the SNR over 81 dB and SNDR over 63 dB can be achieved.