Study of PREB Process in FDSOI

In this paper, photo resist etch back (PREB) process is studied for 22nm node HKMG FDSOI technology. Prior to dummy poly removal (DPR) process, PREB process is introduced in order to overcome pattern loading induced challenge --- the wide and narrow poly gate structure need to be opened separately in order to make sure the dummy gate within the whole chip can be removed thoroughly. Advantages and challenges of this PREB technique will be explained and studied.