Analysis of SET Reconvergence and Hardening in the Combinational Circuit Using a SAT-Based Method

The reconvergence-phenomenon is common in modern circuit design. It occurs when the signal reconvenes at a certain point through multiple sensitized paths. It affects the soft error estimation and hardening. It is complicated to analyze the reconvergence-phenomenon accurately. In this paper, we propose a method based on the satisfiability problem (SAT) to analyze the single event transient (SET) reconvergence-phenomenon in combinational circuits. Our method translates the SET reconvergence issue into an SAT. An SAT solver is used to determine whether the reconvergence-phenomenon could occur and the conditions for its occurrence. According to the results of the solutions, the sensitive nodes in the circuit can be defined. The results show that compared with random hardening, the average soft error rate is reduced 20% by hardening the node selected by our method.