A 6GbpsSerial LinkTransmitter withPre-emphasis

our PLL.Sowe use mediumthreshold PMOS transistors and passive resistance intheloadofdelay cells, interpolators andthe Inthis paper, wepropose anovel6GbpsSATAtransmitter. biasreplica circuit toachieve thisgoal.Thereareseveral Thetransmitter isconstructed byPISO,driver, pre-emphasis and advantages inthis design: PLLfora1V5meter cable. A test chipoftransmitter withPLLand Themediumthreshold voltage (0.24v) PMOS inbiasreplica on-chip termination isimplemented to verify thedesigncircuit (Ml-M4 inFig.2) will workcorrectly evenifVcishigh. methodology. Theoverall circuit isimplemented inTSMC0.1 8um Asaresult, theKvcodecreases because oflarge control voltage 1P6M1.8VCMOS process. Thewholemeasured transmitter jitterrangeofVc.We canalsodecrease theprocess variation by isabout 44psandthepowerconsumption is68mWfor6Gbpscase.increasing thegatelength. Buttheoscillation frequency willnot reach thefrequency weneedifweusenormal threshod (0.51v)