Designing of Low Power Dual Edge - Triggered Static D Flip-Flop with DETFF Logic

The normal D flipflop consumes very high power. So in this paper we enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 90nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to static output-controlled discharge Flip- Flop (SCDFF). SCDFF involves an explicit pulse generator and a latch that captures the pulse signal. The latch structure of SCDFF consists of two static stages. In the first stage, input D is used to drive the pre charge transistor so that node follows D during the sampling period. In this paper conventional and proposed DETFF are presented and compared at same simulation conditions. Therefore the proposed DETFF design is suitable for low power and small area applications.