AES/FPGA Encryption Module Integration for Satellite Remote Sensing Systems: LST-SW case

Satellite remote sensing embedded systems need to be secure to protect data transmission between satellites and the ground station for any threat can affects the hardware of satellite and interception of data, in addition to unauthorized access to satellite system. This research proposes an approach for a secure integration of FPGA Encryption module based on the iterative looping architecture for remote sensing algorithm and especially for the LST-SW algorithm. The target hardware used in this paper is Virtex-5 XC5VLX50T FPGA from Xilinx. Hardware Description Language was used to design the complete system. The analysis of the proposed designed shows that this implementation can achieved a throughput of 1634.71 Mbps and take 6 % of slice in area utilization with one block of RAM.