Compact and Power-Efficient Implementation of Rank-Order Filters Using Time-Domain Digital Computation Technique

A compact and power-efficient digital implementation of rank-order filters compatible with focal-plane image processing has been developed based on a time-domain computation technique. The magnitude of analog pixel intensity is represented as a pulse width in the pulse width modulation scheme, and the rank-order filtering is accomplished using simple digital adders and a binary counter. As a result, a very compact implementation comparable to analog counterparts has been achieved, while preserving the accuracy and programmability of digital implementation. This will enable us to use the rank-order filter as a building block in a parallel processing array. A test chip capable of performing multiple rank-order filtering for up to 16 inputs was designed and fabricated in a 0.35 µm standard complementary metal oxide semiconductor (CMOS) technology. Experimental results have demonstrated the correct operation of the circuit in low-power dissipation of 0.44 mW at 3.3 V with a very compact core size of 0.014 mm2. In addition, the circuit has shown the speed performance of over 260 k ranks/s at 8-bit resolution, which is more than sufficient for use at typical video frame rates.