Timing analysis of an embedded memory: SPSMALL

This paper proposes a high-level formalism, called Abstract Functional and Timing Graph (AFTG), for describing a memory architecture, which combines logical functionality and timing. After translation of the AFTG into the form a timed automaton, we are able to compute the response times of the modeled memory, and check their consistency with the values specified in the datasheet. We also address the problem of finding optimal values of setup timings.