Implementation and integration of a systematic DBPM calibration with PLL frequency synthesis and FPGA

Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM (Beam Position Monitor) processor deteriorates the BPM performance. A systematic solution based on signal source calibration tactics has been carried out to rectify this defect. It is optimized for implementation in FPGA. Mathematical illustrations of the calibration method, hardware and software design and implementation are presented. A signal source circuit using frequency synthesis technique is designed as calibration standard. Data acquisition system using JAVA web technology and Ethernet is introduced. Integrated FPGA implementation code architecture is presented, and experimental test results show that the method implemented in FPGA is feasible. Compared to other methods, our approach can rectify the nonlinearity and asymmetry simultaneously. The whole solution is integrated into the DBPM processor and can be executed online.