Substrate Bias Effect on E-Mode GaN-on-Si HEMT Cos s Losses

Previous work found large Coss losses in GaN-on-Si HEMTs used in soft-switched, MHz-frequency power converters. Here, we use a back-gate bias between the source and Si substrate to investigate the capacitance characteristics of commercially-available GaN HEMTs. The small-signal capacitance is reduced significantly - up to 2 × for a 650 V HEMT and 4× for a 100 V HEMT - indicating that the drain-substrate capacitance is a significant portion of the total output capacitance. This portion of the capacitance appears responsible for trapping-detrapping with time constants on the order of seconds. We verify this by testing the 100 V GaN HEMT in the Sawyer-Tower circuit with negative substrate bias, finding that Coss losses are reduced by up to 30 % compared to the shorted substrate condition. Taken together, our findings indicate that the buffer-substrate stack is likely an important driver of Coss losses in GaN-on-Si HEMTs, and its optimization must be considered to efficiently use GaN HEMTs at high-frequencies. Traditional Coss measurements with the DC bias swept in both directions may give an indication of the relative level of trapping in this stack.