A 10 b 125 MS/s 40 mW pipelined ADC in 0.18 /spl mu/m CMOS

A 10 b 125 MS/s pipelined ADC uses a new front-end circuit and consumes 40 mW from a 1.8 V supply. The ADC is implemented in a 0.18 /spl mu/m CMOS process and has an active area of 1.1/spl times/0.6 mm/sup 2/. Measured INL (integral nonlinearity) and DNL (differential nonlinearity) are within /spl plusmn/0.7 LSB, and /spl plusmn/0.5 LSB, respectively. Peak SNDR is 53.7 dB with a 2 MHz input.