STT-MRAM error correction technology based on LDPC coding

Spin transfer magnetoresistive random access memory (STT-MRAM) shows potential applications with the properties of non-volatility, low power consumption and high write/read speed. With the maturity of the STT-MRAM process, it has gradually entered the mass production stage. Reliability will be an important factor limiting the development of this device. Error correction technology is highly required to be developed on this specific memory circuit. In this paper, a combination of low density parity check (LDPC) is used on STT-MRAM, in which the encoding constructs a no 4-girth check matrix. In its fulfillment, the decoded method combines soft decision and hard decision. The simulation results demonstrate that the LDPC shows promising application scenario for STT-MRAM error correction, especially for large-capacity storage arrays.Spin transfer magnetoresistive random access memory (STT-MRAM) shows potential applications with the properties of non-volatility, low power consumption and high write/read speed. With the maturity of the STT-MRAM process, it has gradually entered the mass production stage. Reliability will be an important factor limiting the development of this device. Error correction technology is highly required to be developed on this specific memory circuit. In this paper, a combination of low density parity check (LDPC) is used on STT-MRAM, in which the encoding constructs a no 4-girth check matrix. In its fulfillment, the decoded method combines soft decision and hard decision. The simulation results demonstrate that the LDPC shows promising application scenario for STT-MRAM error correction, especially for large-capacity storage arrays.