Effect of I/O oxide process optimization on the nbti dependence of T inv scaling for a 20 nm bulk planar Replacement Gate process

We present results on the beneficial effect of an additional thermal treatment on the NBTI aging of an I/O thick oxide process in 20nm Replacement Metal Gate (RMG) High-k Metal Gate (HKMG) technology. It is shown that for an as-grown thermal thick oxide gate process, the NBTI induced device threshold voltage shift (ΔV th ) scales as T inv -2 when stressed at a given gate voltage V g . On the other hand, the ΔV th dependence on V g is ΔV th ~ (V g ) 4 for a given T inv . These findings seem to be apparently inconsistent with well known power law NBTI dependence on E ox (~ (V g /T inv )). The expected NBTI dependence on E ox (ΔV th ~ (V g /T inv ) 4 ) is recovered when the as-grown thermal thick oxide is treated with an additional high temperature anneal. We have evaluated the NBTI induced ΔV th time evolution, its recovery behavior, temperature and voltage dependence under DC and AC bias stress conditions with and without the oxide thermal treatment. Our observations over the two gate stack processes (as-grown I/O oxide with and without anneal treatment) support the NBTI physical picture of two uncorrelated contributions to the NBTI damage. Namely, shallow hole trap activation in process induced pre-existing (before stress) traps as well as deep hole traps and/or interface states generation. The last component is quasi permanent and is dominant in both gate stack processes. In particular, for the as-grown I/O oxide the NBTI damage is mainly due to an increase contribution of the quasi permanent component with increasing T inv. This unexpected T inv dependence is reduced by the additional anneal treatment. The implication of these findings on the NBTI characterization and modeling will be discussed.