The SYNC Chip in the Electronics Architecture of the LHCb Muon Detector

We present a custom integrated circuit, named SYNC, which plays a fundamental role in the time alignment of the LHCb Muon Detector and consequently in the trigger performance. The SYNC is realized in IBM 0.25 μm technology, using radiation-hardening layout techniques. SYNC receives data from the muon detector front-end electronics synchronizing them with the 40.08 MHz LHC clock. The data are tagged with the correct Bunch-Crossing identifier, output to the trigger system and stored in internal memories. The chip integrates 8 time to digital converters with a resolution up to 1 ns to measure the time phase of the input signals with respect to the system clock period. A histogram block can build real time spectra from the TDCs output. A I 2 C interface is implemented to configure and control the device, while a JTAG interface is integrated for boundary-scan purpose. We describe the circuit architecture, its internal blocks and its main modes of operation. Measurements performed on final prototypes are also reported.