A 0.12mm 2 5Gbps receiver with a level shifting equalizer and a cumulative-histogram-based adaptation engine

This paper presents a 0.12mm 2 5Gbps receiver with an adaptive equalizer. To minimize the equalizer area, a source-input front-end that performs level shifting and equalizing is proposed. In addition, an adaptive equalization algorithm is also proposed, which finds an optimal equalizer setting by observing the cumulative histogram of the equalizer-output amplitude, reducing the hardware cost of the adaptation. A test chip was designed and fabricated in a 65nm CMOS technology. It achieved an equalization of a 20dB transmission loss with a BER of less than 10 −12 , while consuming 36mW from a 1.2V power supply.