The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-Passivated Ge pMOSFETs

Recently, the best 65 nm Ge p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET) performance has been reported with a standard Si complementary metal-oxide-semiconductor HfO 2 gate stack module. The Ge passivation is based on a thin, fully strained epitaxial Si layer grown on the Ge surface. We investigate in more detail how the device performance (hole mobility, I on , D it, V t , etc.) depends on the characteristics of this Si layer. We found that surface segregation of Ge through the Si layer takes place during the growth, which turns out to be determining for the interfacial trap density and distribution in the finalized gate stack. Based on a better understanding of the fundamentals of the Si deposition process, we optimize the process by switching to another Si precursor and lowering the deposition temperature. This results in a 4 times lower D it and improved device performance.