Investigation of Different Conduction States on the Performance of NMOS-Based Power Clamp ESD Device

This article investigates the effects of different gate coupling voltage and gate voltage duration on electro-static discharge (ESD) performance of several NMOS-based power rail protection devices. Through simulation and transmission line pulse (TLP) test, it is found that there are two modes in the conduction process of the main clamping NMOS: channel conduction state and parasitic NPN conduction state. Different gate voltage and duration bring the two conduction states different proportions in the whole working process, which give the device very different robustness. The results show that under the condition of small gate voltage and long duration and the condition of large gate voltage and short duration, the device can achieve optimal performance because the trigger voltage can be reduced, and the parasitic NPN can be turned on in time to release most of the current.