Wet etched 3-level silicon interposer for 3 dimensional embedding and connecting of opto-electronic dies and CMOS ICs

Ultra-compact optical sub-modules for parallel optical interconnects are demonstrated based on a 3-level silicon interposer, which is fabricated through a low cost wet etching process. Using three steps of wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping optical and electrical dies, and opening optical through silicon vias. In order to reduce thermal coupling between CMOS and GaAs dies, a 50 μm thermal isolation air gap is formed between dies as part of the assembly concept, and thermal simulations and experiments are carried to validate its effectiveness. Based on this 3D packaging concept, compact 4 mm × 6 mm, 10 Gbps 12-channel transmitter and receiver sub-modules are fully assembled and tested. Clear and uniform eye patterns for both modules are captured at 10 Gbps and 15 Gbps for every channel. Bit error rate (BER) testing is also performed. Both transmitter and receiver sub-modules show uniform BER curves, with receiver sensitivity spreading less than 1 dB at a BER lower than 10-12. Also, crosstalk for both modules is tested, yielding only a 0.1 dB and 0.8 dB additional penalty for transmitter and receiver respectively.