An algorithm adapted autonomous controlling concept for a parallel single-chip digital signal processor

The controlling concept of a parallel homogenous SIMD video signal processor has been derived from the requirements of data dependent image processing algorithms. The processor, called HiPAR-DSP, consists of an array of 16 datapaths, local memories for each data-path, a shared memory with concurrent access in shape of a matrix and a central RISC controller. A three stage execution autonomy was implemented, consisting of conditional instructions, conditional skip of instructions by the data paths and global evaluation of local conditions by the central controller. This allows data parallel execution of data dependent medium- and high-level algorithms with very low controlling overhead. The HiPAR-DSP requires 300 ns to perform a tree search on a 1024 element list and 10.5 ms for the connected component labeling of a 512/spl times/512 pel image. The processor operates at a clock frequency of 100 MHz and requires a silicon area of 250 mm/sup 2/ in a 0.5 /spl mu/m CMOS standard cell technology.