A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming

A high density, Programmable Logic Device (PLD) family developed for hot socketing and high performance is discussed. The family is fabricated on a 0.32 um quadruple layer metal process. The largest family member is a 512 macrocell part with typical pin to pin delays of 4.9 ns. The design techniques and testing methodology to guarantee safe hot socketing are described. Streamlined In System Programming (ISP) and circuits used to configure EEPROM cells with a 3.3-V supply are also discussed.